Books, Original Papers & Review Papers- WAIDYASOORIYA HASITHA MUTHUMALA -
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[B]:Books [O]:Original Papers [R]:Review Papers
total:35
[2018]
1.[O] Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems.[Supercomputing Frontiers - 4th Asian Conference, SCFA 2018, Singapore, March 26-29, 2018, Proceedings,(2018),146-155]Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada
10.1007/978-3-319-69953-0_9
[2017]
2.[O] OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology.[IEEE Transactions on Parallel and Distributed Systems,28(5),(2017),1390-1402]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunpike Tatsumi, Masanori Hariyama
10.1109/TPDS.2016.2614981
3.[O] OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions.[International Journal of Reconfigurable Computing,2017,(2017),Article ID 6817674-]Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
10.1155/2017/6817674
4.[O] An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL.[International Journal of Networked and Distributed Computing,5(1),(2017),52-61]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
10.2991/ijndc.2017.5.1.6
5.[O] An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL..[IJNDC,5(1),(2017),52-61]Hasitha Muthumala Waidyasooriya,Masanori Hariyama,Kota Kasahara
6.[O] OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions..[Int. J. Reconfig. Comp.,2017,(2017),6817674:1-6817674:11-]Array,Array,Array,Array
7.[O] Architecture of an FPGA accelerator for LDA-based inference..[18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017, Kanazawa, Japan, June 26-28, 2017,(2017),357-362]Taisuke Ono,Hasitha Muthumala Waidyasooriya,Masanori Hariyama,Tsukasa Ishigaki
[2016]
8.[O] FPGA architecture for 3-D FDTD acceleration using open CL.[Progress in Electromagnetic Research Symposium (PIERS),(2016),4719]H. M. Waidyasooriya, M. Hariyama, Y. Ohtera
9.[O] FPGA-Based Deep-Pipelined Architecture for FDTD Acceleration Using OpenCL”, 15th IEEE/ACIS International Conference on Computer and Information Science.[15th IEEE/ACIS International Conference on Computer and Information Science,(2016),109-114]Hasitha Muthumala Waidyasooriya, Masanori Hariyama
10.[O] Architecture of an FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL.[15th IEEE/ACIS International Conference on Computer and Information Science,(2016),115-119]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
11.[O] Hardware-Acceleration of Short-read Alignment Based on the Burrows-Wheeler Transform.[IEEE Transactions on Parallel and Distributed Systems,27(5),(2016),1358-1372]Hasitha Muthumala Waidyasooriya, Masanori Hariyama
10.1109/TPDS.2015.2444376
12.[O] Hardware-Oriented Succinct-Data-Structure for Text Processing Based on Block-Size-Constrained Compression.[International Journal of Computer Information Systems and Industrial Management Applications,8(11),(2016),1-11]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
13.[O] Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform..[IEEE Trans. Parallel Distrib. Syst.,27(5),(2016),1358-1372]Array,Masanori Hariyama
14.[O] FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL..[15th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2016, Okayama, Japan, June 26-29, 2016,(2016),1-6]Hasitha Muthumala Waidyasooriya,Masanori Hariyama
15.[O] Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL..[15th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2016, Okayama, Japan, June 26-29, 2016,(2016),1-5]Hasitha Muthumala Waidyasooriya,Masanori Hariyama,Kota Kasahara
[2015]
16.[O] Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators.[IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES,E98A(12),(2015),2658-2669]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
10.1587/transfun.E98.A.2658
http://gateway.isiknowledge.com/gateway/Gateway.cgi?&GWVersion=2&SrcAuth=TohokuUniv&SrcApp=TohokuUniv&DestLinkType=FullRecord&KeyUT=WOS:000367096000036&DestApp=WOS
17.[O] Hardware-Oriented Succinct-Data-Structure based on the Block-Size-Constrained Compression.[International Conference on Soft Computing and Pattern Recognition(SoCPaR),(2015),136-140]Hasitha Waidyasooriya, Daisuke Ono, Masanori Hariyama
10.1109/SOCPAR.2015.7492797
18.[O] Hardware-oriented succinct-data-structure based on block-size-constrained compression..[7th International Conference of Soft Computing and Pattern Recognition, SoCPaR 2015, Fukuoka, Japan, November 13-15, 2015,(2015),136-140]Hasitha Muthumala Waidyasooriya,Daisuke Ono,Masanori Hariyama
[2014]
19.[O] FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation..[J. Computational Engineering,2014,(2014),634269:1-634269:8-]Hasitha Muthumala Waidyasooriya,Masanori Hariyama,Array,Array
20.[O] Efficient Data Transfer Scheme Using Word-Pair-Encoding-Based Compression for Large-Scale Text-Data Processing.[2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS),(2014),639-642]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
10.1109/APCCAS.2014.7032862
http://gateway.isiknowledge.com/gateway/Gateway.cgi?&GWVersion=2&SrcAuth=TohokuUniv&SrcApp=TohokuUniv&DestLinkType=FullRecord&KeyUT=WOS:000361128200155&DestApp=WOS
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